1. Field of the Invention
The present invention relates to a fabrication method for a semiconductor package substrate and a semiconductor package, and more particularly, to a fabrication method for a column lead package (CLP).
2. Background of the Related Art
FIG. 1 shows a cross-sectional view of a Quad Flat Package, in which a semiconductor chip 3 is mounted on a paddle 2 of a lead frame 1. The chip 3 is electrically connected to inner leads 1a of the lead frame 1 by bonding wires 4, and the entire whole body 5 except for outer leads 1b is encapsulated by an epoxy molding compound.
The Quad Flat Package is disadvantageous since precise alignment of the outer leads 1b onto the bonding pads of a printed circuit board (PCB) is difficult. Further, the outer leads 16 may be damaged or deformed due to external impacts during the lead-forming process in which the outer leads 16 are bent into prescribed shapes. The repairing of the chip package defects when mounted on a PCB has been troublesome, and simplification of the fabrication process has been difficult.